PCI表面配置資料格式

Format of PCI Configuration Data:

Offset Size Description
 00h WORD vendor ID (read-only)
FFFFh returned if requested device non-existent
 02h WORD device ID (read-only)
 04h WORD command register
 06h WORD status register
 08h BYTE revision ID
 09h  3 BYTEs class code
bits 7-0: programming interface
bits 15-8: sub-class
bits 23-16: class code
 0Ch BYTE cache line size

 0Dh BYTE latency timer
 0Eh BYTE header type
bits 6-0: header format
00h other
01h PCI-to-PCI bridge
02h PCI-to-CardBus bridge
bit 7: multi-function device
 0Fh BYTE Built-In Self-Test result
---header type 00h---
 10h DWORD base address 0
(OpenHCI) base address of host controller registers
 14h DWORD base address 1
 18h DWORD base address 2
 1Ch DWORD base address 3

 20h DWORD base address 4
 24h DWORD base address 5
 28h DWORD CardBus CIS pointer (read-only)
 2Ch WORD subsystem vendor ID or 0000h
 2Eh WORD subsystem ID or 0000h
 30h DWORD expansion ROM base address
 34h BYTE offset of capabilities list within configuration space (R/O)
(only valid if status register bit 4 set)
 35h  3 BYTEs reserved
 38h DWORD reserved
 3Ch BYTE interrupt line

00h = none, 01h = IRQ1 to 0Fh = IRQ15
 3Dh BYTE interrupt pin (read-only)
(00h = none, else indicates INTA# to INTD#)
 3Eh BYTE minimum time bus master needs PCI bus ownership, in 250ns units
(read-only)
 3Fh BYTE maximum latency, in 250ns units (bus masters only) (read-only)
 40h 48 DWORDs varies by device
---header type 01h---
 10h DWORD base address 0

 14h DWORD base address 1
 18h BYTE primary bus number (for bus closer to host processor)
 19h BYTE secondary bus number (for bus further from host processor)
 1Ah BYTE subordinate bus number
 1Bh BYTE secondary latency timer
 1Ch BYTE I/O base
 1Dh BYTE I/O limit
 1Eh WORD secondary status
 20h WORD memory base
 22h WORD memory limit
 24h WORD prefetchable memory base

 26h WORD prefetchable memory limit
 28h DWORD prefetchable base, upper 32 bits
 2Ch DWORD prefetchable limit, upper 32 bits
 30h WORD I/O base, upper 16 bits
 32h WORD I/O limit, upper 16 bits
 34h DWORD reserved
 38h DWORD expansion ROM base address
 3Ch BYTE interrupt line
 3Dh BYTE interrupt pin (read-only)
 3Eh WORD bridge control
 40h 48 DWORDs varies by device